Computer Science
A-Level Computer Science
OCR
The Characteristics of Contemporary Processors, Input, Output and Storage
[ 1.1.1 ]
what is the function of the Arithmetic Logic Unit (ALU) ?
completes all arithmetic and logic functions
results are often stored in general-purpose registers (e.g. the ACC)
give three examples of operations the ALU performs.
arithmetic operations on fixed/floating point numbers (e.g. ADD, SUBTRACT, MULTIPLY or DIVIDE)
bitwise shift operations
boolean logic operations (e.g. comparisons, AND, OR, NOT or XOR)
what is the function of the Control Unit (CU) ?
coordinates all activities of the CPU
accepts and decodes instructions
sends memory read/write requests to RAM along the control bus
sends control signals
e.g bus requests/grants, or interrupt requests
makes extensive use of the status registers and clock
communicates with all elements of the CPU
define a register.
registers are small memory cells that operate at a very high speed, they are used to temporarily store data
what is the function of the Program Counter (PC) ?
holds the address of the next instruction to be executed
this could be:
the next instruction in a sequence
an address to jump to, if the previous instruction was to branch (copied from the CIR)
at the start of every FDE cycle, the instruction in the PC is copied to the MAR
what is the function of the Memory Data Register (MDR) ?
used to temporarily store data/instructions that are to be written to memory, or have been read from memory
contents of MDR are copied to the CIR (if MDR contains an instruction)
acts as a buffer
what is the function of the Memory Address Register (MAR) ?
holds the address of a memory location from which data or an instruction is to be fetched, or which data is to be written to
sends this address to memory down the address bus
where does the address in the MAR come from?
it is either the address of an instruction (to be accessed in memory) sent from PC…
or the address of data (to be accessed in memory) sent from CIR
what is the function of the accumulator (ACC) ?
data and control information often stored here
stores the results of operations performed in the ALU
describe two ways the accumulator is used.
temporary storage for data being processed during calculations
I/O in processor, used as a buffer
what is the function of the Current Instruction Register (CIR) ?
holds the current instruction being executed
contents of MDR are copied to the CIR (if MDR contains an instruction)
contains the opcode and operand(s) of the instruction
what is a bus?
buses are a set of parallel wires which connect two or more components inside the CPU
what does the ‘width‘ of a bus represent?
the width of the bus is the number of parallel wires the bus has:
the width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any given time
buses are typically 8, 16, 32 or 64 wires wide
what is the function of the data bus?
a bi-directional bus that transports data and instructions (in binary) between components
what is the function of the address bus?
transmits memory addresses specifying where data or instructions are to be sent to/retrieved from
what is the function of the control bus?
transmits control signals between internal/external components
coordinates the use of the address and data buses
provides status information between system components
what is a bus request?
a control signal that shows that a device is requesting the use of the data bus
what is a bus grant?
a control signal that shows that the CPU has granted access to the data bus
what is a memory write request?
a control signal that requests that data is written into the addressed location using the data bus
what is a memory read request?
a control signal that requests that data is read from a specific location to be placed onto the data bus
what is an interrupt request?
a control signal that shows that a device is requesting access to the CPU
what is the Fetch Decode Execute cycle?
the cycle that a CPU follows to process and execute a instruction
what occurs during the fetch stage?
address of the next instruction is copied from PC to MAR
contents of MAR are sent along the address bus to memory, where it waits to receive a signal from the control bus
the data/instruction held in the corresponding memory address is copied to MDR by the data bus
if MDR holds an instruction, its contents are copied to CIR
PC is incremented by 1
what occurs during the decode stage?
the instruction in CIR is split into opcode and operand
the instruction is decoded in the decode unit
what occurs during the execute stage?
the instruction is executed, for example…
performing arithmetic operations in the ALU
storing the contents of the accumulator in a memory address in RAM
what is clock-speed?
clock speed is the number of clock cycles completed per second
clock speed is determined by the system clock (an electronic device which generates signals, switching periodically between 0 and 1)
how does the clock regulate CPU operations?
all processor activities begin on a clock pulse, and each CPU operation starts as the clock changes from 0 to 1
how is clock-speed measured?
measured in GigaHertz (GHz)
one GHz is one billion instructions fetched per second
what is a core?
an independent processor that is able to run its own FDE cycle
what are the benefits of using a computer with multiple cores? [EDIT]
computers with multiple cores can complete multiple FDE cycles at once
what are the drawbacks of using a computer with multiple cores?
a computer with dual cores can theoretically complete tasks twice as fast as a computer with a single core, however..
not all programs are able to utilise multiple cores efficiently as they have not been designed to do so
inter-core communication also requires processor time
what is cache memory?
cache memory is located on or near the CPU
much faster to access than RAM
instructions fetched from main memory are copied to the cache, so if required again, they can be accessed quicker
as cache fills up, unused instructions are replaced
what is pipelining?
pipelining is the process of completing the FDE cycles of separate instructions simultaneously and holding appropriate data in a buffer in close proximity to the CPU until it’s required
it aims to reduce the amount of the CPU which is kept idle
it is separated into instruction pipelining and arithmetic pipelining
what is instruction pipelining?
separating out the instruction into fetching, decoding, and executing
what is arithmetic pipelining?
breaking down the arithmetic operations and overlapping them as they are performed
why can pipelining sometimes become inefficient?
pipelining is inefficient when programs contain lots of branching
as each time a program branches the processor will have to ‘flush the pipe’
describe harvard processor architecture.
instructions and data stored in separate memory units
each has its own bus
reading and writing data can be done at the same time as fetching an instruction
used in RISC processors
describe von neumann processor architecture?
shared memory space for data and instructions
built on the ‘stored program’ concept
instructions and data stored in the same format
a single control unit follows a linear FDE cycle
one instruction at a time
what are the advantages of von neumann architecture?
cheaper to develop, control unit is easier to design
programs can be optimised in size
what are the advantages of harvard architecture?
quicker execution as data and instructions can be fetched in parallel
memories can be different sizes, makes efficient use of space